Download Arithmetic Built-In Self-Test for Embedded Systems by Janusz Rajski PDF

By Janusz Rajski

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Extra resources for Arithmetic Built-In Self-Test for Embedded Systems

Example text

These registers are serially connected with the internal scan path, as well as with a test generator and a test-response compactor. The last two blocks are implemented by means of the LFSRs. The design also includes an on-chip monitor acting as a BIST controller and an error detection circuitry employed to compare the final value in the compactor with a good signature. The BIST circuitry operates in such a way that input vectors produced by the LFSR are applied serially to the primary inputs and internal nodes of the CUT through the boundary scan and internal scan flip-flops.

3 Error Models and Aliasing How likely is it that a fault will generate a signature identical to a fault-free signature? To answer this fundamental question, numerous approaches have been proposed to derive a closed-form solution for the aliasing probability. Since detailed circuit simulation may not be practical, the aliasing probability is often estimated based on probabilistic models of erroneous sequence generated by faulty circuits. These error models reflect some basic features of the CUT and can be generally divided into two groups: those describing single streams of bits for single-input compaction schemes, and models used for multiple-input compactors.

5) Yet another property of the vectors generated by LFSRs is that they appear to be randomly ordered. In fact, they behave randomly with respect to many statistical tests, and hence, the theoretical results regarding expected test length and fault coverage derived above can be replaced for purely random testing, assuming sufficiently large LFSRs. Each test vector is now chosen out of N —> ∞ different vectors and immediately replaced. Again, let us first consider the probability of detecting a fault with v random test vectors, assuming that the detection probability is p.

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