By Maggie Xiaoyan Cheng
This e-book constitutes the completely refereed post-conference lawsuits of the 3rd overseas convention on Nano-Networks, Nano-Net, held in Boston, MS, united states, in September 2008. The 17 revised complete papers awarded including five invited shows have been rigorously reviewed and chosen. The papers deal with the total spectrum of Nano-Networks and spans topis like modeling, simulation, statdards, architectural features, novel details and graph idea features, machine physics and interconnects, nanorobotics in addition to nano-biological structures.
Read or Download Nano-Net: Third International ICST Conference, NanoNet 2008, Boston, MS, USA, September 14-16, 2008. Revised Selected Papers (Lecture Notes of the Institute ... and Telecommunications Engineering) PDF
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Extra resources for Nano-Net: Third International ICST Conference, NanoNet 2008, Boston, MS, USA, September 14-16, 2008. Revised Selected Papers (Lecture Notes of the Institute ... and Telecommunications Engineering)
Process variation leads to large variation in delay, which may cause incorrect function of the system due to missed deadlines and also makes it diﬃcult to achieve high performance. We are using WISP-0, a simple 5-stage streaming processor design, based on the NASIC nanoscale fabric architecture, to explore the impact of process variation on circuits with built-in fault resilience. NASIC is a tiled 2-D grid-based circuit fabric using a dynamic circuit style. For more information on NASIC and WISP-0, please see .
The Au electrodes were planarized by CMP and ﬁnally the SiO2 spacer ﬁlm between the gold electrodes is selectively etched oﬀ using HF (e). The deposited Silicon Nitride layer will act as etch stop of this etching process and also serves as an isolator between the gold electrodes and the Si wafer. Here the use of deposited oxide thin ﬁlm to deﬁne the separation between gold electrodes allows the fabrication of capacitive structures with electrode separations lower than the resolution limit of optical or e-beam lithography.
We use the WISP-0 design in our simulations so as to gauge the eﬀects on a processor. In order to capture the typical behavior, we use the Monte Carlo method, picking the parameter values used for each wire and transistor from a distribution. We use a Gaussian distribution with a variation of M. ): NanoNet 2008, LNICST 3, pp. 26–27, 2009. c ICST Institute for Computer Sciences, Social Informatics and Telecommunications Engineering 2009 Impact of Process Variation in Fault-Resilient Streaming Nanoprocessors 27 3σ = 60% for each parameter, which is higher than reported by nanoscale device and materials researchers.