By Michael Keating
Silicon know-how now permits us to construct chips which include hundreds of thousands of transistors. This expertise not just supplies new degrees of method integration onto a unmarried chip, but additionally offers major demanding situations to the chip clothier. consequently, many ASIC builders and silicon owners are re-examining their layout methodologies, trying to find how you can make powerful use of the large numbers of gates now on hand.
those designers see present layout instruments and methodologies as insufficient for constructing million-gate ASICs from scratch. there's huge strain to maintain layout crew dimension and layout schedules consistent while layout complexities develop. instruments aren't supplying the productiveness earnings required to maintain velocity with the expanding gate counts on hand from deep submicron expertise. layout reuse - using pre-designed and pre-verified cores - is the main promising chance to bridge the distance among on hand gate-count and clothier productiveness.
Reuse technique handbook for System-On-A-Chip Designs, moment Edition outlines a good method for developing reusable designs to be used in a System-on-a-Chip (SoC) layout method. Silicon and gear applied sciences movement so fast that no unmarried technique gives you an everlasting strategy to this hugely dynamic challenge. as an alternative, this handbook is an try to catch and incrementally increase on present top practices within the undefined, and to offer a coherent, built-in view of the layout procedure. Reuse technique handbook forSystem-On-A-Chip Designs, moment Edition should be up-to-date usually due to altering know-how and stronger perception into the issues of layout reuse and its function in generating top of the range SoC designs.
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Extra resources for Reuse Methodology Manual: For System-on-a-Chip Designs
Too many hard macros, or macros with the wrong aspect ratio, can make the chip unroutable or unacceptably big, or can create unacceptable delays on critical nets. 4 Clock Distribution Rule - The design team must decide on the basic clock distribution architecture for the chip early in the design process. The size of the chip, the target clock frequency, and the target library are all critical in determining the clock distribution architecture. To date, most design teams have used a balanced clock tree to distribute a single clock throughout the chip, with the goal of distributing the clock with a low enough skew to prevent hold-time violations for flip-flops that directly drive other flip-flops.
Locality - Problems are easiest to find and solve when you know where to look. Making timing and verification problems local rather than global has a huge payoff in reducing design time and improving the quality of a design. Careful block and interface design is essential for achieving this locality. The authors, and many designers like us, learned these principles while designing large systems, and often learned them the hard way. For example (Mike speaking here), one of my first jobs was designing very large (hundreds of boards, each with hundreds of chips) ECL systems.
A number of companies and standards committees have attempted to standardize buses and interfaces, with mixed results. In this section, we discuss some of the issues facing designers attempting to design IP for multiple environments and SoC designers attempting to integrate IP from various (incompatible) sources. 1 Basic Interface Issues The version of our canonical design shown in Figure 3-5 shows a common configuration for buses on an SoC design. A hierarchy of buses is used to deal with the different bandwidth requirements of the various blocks in the system.